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- いいね！2
Kara Pesavento
@gmnroad
IT Jungle: IBM to Divulge Power8 Processor Secrets at Hot Chips http://t.co/8Oxs0kMhLj
2013-08-27 01:10:20
Victor Grund
@vgrund
#IBM To Divulge #Power8 Processor Secrets At Hot Chips http://t.co/cGTgs3PeKW
2013-08-27 01:35:53
ｈｒｋ先生
@Prof_hrk
午後のIBMセッション、POWER8から。Austinの人。2，4，8が選べるFlexible SMTがFeature. 12コア、64K Data, 32K I cache. HTM, VMMサポート。
2013-08-27 05:36:05
ｈｒｋ先生
@Prof_hrk
22nm SOI, eDram 650mm2. 512K SRAM L2, 96MB eDRAM L3, off chip eDRAM L4. Memory BW 230GB/s, CAPI (coherent accelerator Processor Interface)
2013-08-27 05:38:29
ｈｒｋ先生
@Prof_hrk
core -> SMT8, 8 dispatch, 10 issue, 16 ex pipe (2FXU, 2LSU, 2LU, 4 FPU, 2 VMX, 1 Crypto, 1DFU, 1CR, 1BR, 4x translation cache. プリフェッチ強化。
2013-08-27 05:40:35
Rick Merritt
@rickbmerritt
#IBM Power 8 packs 12 cores, 96 MBytes shared L3, crypto, etc in 650mm2 22nm chip #hotchips http://t.co/cZPWvQyZYC
2013-08-27 05:42:25
Daniel Bowers
@Daniel_Bowers
IBM introducting POWER8: 12 cores, 8-way SMT #HC25 http://t.co/vSSf7mHlIK
2013-08-27 05:44:51
拡大
Jan Gray
@jangray
US patent 7,895,579 "automated method & system for collecting & reporting performance profiles" -- ideas that don't ship never to heaven go
2013-08-27 05:45:31
Daniel Bowers
@Daniel_Bowers
IBM POWER8 core. More threads, larger L2 data cache. "More efficient use of execution units." #HC25 http://t.co/aEylzby5Ip
2013-08-27 05:46:58
拡大
ｈｒｋ先生
@Prof_hrk
1.6xシングルスレッド性能、2x SMT性能。なおクロックは4GHｚ。メモリモジュールへDedicatedなメモリバッファチップとモジュール構成。 IOはPCIEGEN3x16がOnchip
2013-08-27 05:50:32
Daniel Bowers
@Daniel_Bowers
IBM: POWER8 to have 2.5x memory bandwidth, 2.5x Java performance, 2.25x integer performance of POWER7+ on a socket-to-socket basis. #HC25
2013-08-27 05:50:39
Jan Gray
@jangray
#HotChips Power8 CAPI Coherent Accelerator Processor Interface. Clever accomodation for FPGA accel'rs. Heavy lifting in CAPProxy core on P8.
2013-08-27 05:55:31
Jim McGregor
@TekStrategist
Hot Chips: IBM Power8 - a 12 core, 650mm2, and 96MB L3 cache behemoth with up to 2.5x the performance of the Power7. A big iron workhorse.
2013-08-27 05:59:33
Daniel Bowers
@Daniel_Bowers
IBM: POWER8 decodes up to 16 instructions per clock. #HC25
2013-08-27 06:00:13
Daniel Bowers
@Daniel_Bowers
Details on POWER8 "CAPI" : Coherence Attach Processor Interface #HC25 http://t.co/s1IONJ1FBq
2013-08-27 06:01:26
拡大
Daniel Bowers
@Daniel_Bowers
IBM: POWER8 will use about the same power as POWER7. #HC25
2013-08-27 06:05:37
ｈｒｋ先生
@Prof_hrk
6コア、2.75GTr, 598 mm2. 大きい！コアも大きいが半分くらいがL2キャッシュ。 POWER8との対比が興味深い。
2013-08-27 06:25:59
Justin Bowyer
@JustinBowyer
IBM preps its massive 12-headed Power 8 chip: IBM's Power series chips are one of the last bastio... http://t.co/yC7LHbU60X #venturebeat
2013-08-27 06:41:18
Localize
@Localize
Venture Beat: IBM preps its massive 12-headed Power 8 chip http://t.co/MZmwkgAtMu
2013-08-27 06:48:12
electronics
@electronicPR
IBM preps its massive 12-headed Power 8 chip - VentureBeat http://t.co/Cm5hZLmaER
2013-08-27 06:51:52
Vincent Patel
@Vincent__Patel
#in IBM preps its massive 12-headed Power 8 chip: IBM's Power series chips are one of the last bastions standi... http://t.co/4dBIuRMzBS
2013-08-27 06:58:09
Emma Parkes
@emmafparkes
IBM to license Power chip design to Google, others - Computerworld (blog) http://t.co/nERzTC07K5
2013-08-27 07:08:55
VoipTown Voip Forum
@voiptown
[ Press Release]IBM preps its massive 12-headed Power 8 chip http://t.co/YrDQL1gYST
2013-08-27 07:22:30
Kazunori Sato
@kazunori_279
HotChips25のIBM POWER8発表スライドより。CAPIっていうインタフェースを通じて外部のFPGAやASICとキャッシュ共有できるみたい。ZynqのARM/FPGA間L2キャッシュ共有に近い使い方ができると思われ。 http://t.co/hYOXSm28gs
2013-08-27 09:51:15